Manufacturing imperfections in the integrated circuit fabrication process result in undesired variations in the behavior of an integrated circuit from one die to another. These manufacturing or process variations can typically be classified into two types: global variations and intra-die variations. Global variations are variations from one die to another. In this case, the differences between transistors on the same die are as designed for the nominal case. For example, two transistors that are designed to be exactly identical will be identical on any one die, but all the transistors on a single die will shift together to some non-nominal process corner. In other words, the parameters of all the transistors within a single die are perfectly correlated. In the second case of intra-die variations, there is some independent variation from one transistor to another, resulting in partially correlated transistors on the same die. Furthermore, this correlation tends to be very high for neighboring transistors and decreases with the separating distance between any two transistors. As a result, this is spatially correlated intra-die variation. Typically all transistors within a single logic gate are assumed to be perfectly correlated, and this intra-die variation is modeled as inter-gate variation. In such a representation, if there are 1 million logic gates in an integrated chip, there will be 1 million random variables for each transistor parameter (e.g., channel length, threshold voltage, or the like).
Statistical static timing analysis (SSTA) is one critical application that has emerged as an essential tool for dealing with this statistical uncertainty in nanoscale designs. Prevailing SSTA methods, which are referred to as model based methods, typically exploit some simplifications to make the computation tractable. The most adopted implementations typically assume a linear dependence of gate delays (i.e., slew rates) on the statistical parameters (e.g., channel length, gate width, threshold voltage, or the like) for gates. This linear model enforces a severe approximation of the max( ) operator used to compute the worst case delay of any gate to maintain the linear dependence of the circuit delay on all statistical parameters. Early implementations also required the assumption of normally distributed statistical parameters. This leads to errors in the estimates of the circuit delay (or slack) distributions. Extensions to nonlinear gate models and/or non-normal distributions have been proposed. However, these extensions usually result in higher computation cost that might not scale cheaply with an increasing number of parameters, which is a trend expected for upcoming technologies. As a result, these extensions seem not to have yet found wide adoption in practice. Therefore, there is a need for a method and system for rapidly modeling and simulating intra-die variations in an integrated circuit.